1. Field of the Invention
The present invention relates generally to a channel interleaving/deinterleaving apparatus and a control method thereof, and in particular to a channel interleaving/deinterleaving apparatus in a communication system using a Low Density Parity Check (LDPC) code and a control method thereof.
2. Description of the Related Art
The rapid growth of a mobile communication system has created a need for development of technology for transmitting a large amount of data in wireless networks in a capacity level parallel to that of wired networks. This requires a high-speed, high-capacity communication system capable of processing and transmitting various information such as image data, radio data, as well as voice-centric service. Therefore, it is necessary to increase the system transmission efficiency using an appropriate channel coding scheme in order to improve the system performance. However, a mobile communication system inevitably experiences errors occurring due to a number of factors including noise, interference, fading, and channel conditions during data transmission. These errors may cause a loss of information data.
Reliability of the mobile communication system can be improved by using various error-control schemes based on channel characteristics to reduce the information data loss due to the occurrence of errors. The most widely used error-control technology uses an error-correcting code. A description will now be given of a Turbo Code and a Low Density Parity Check (LDPC) code serving as typical error-correcting codes.
It is well known that the Turbo Code is superior in performance gain to a Convolutional Code conventionally used for error correction, at the time of high-speed data transmission. The Turbo Code is advantageous in that it can efficiently correct an error caused by noise occurring in a transmission channel, thereby improving the reliability of data transmission. The LDPC code can be decoded using an iterative decoding algorithm based on a sum-product algorithm on a factor graph. Given that a decoder for the LDPC code uses the sum-product algorithm-based iterative decoding algorithm, it has a lower complexity than a decoder for the Turbo Code. In addition, the decoder for the LDPC code is more easily implemented as a parallel processing decoder, as compared with the decoder for the Turbo Code.
Shannon's channel coding theorem shows that reliable communication is possible only at a data rate not exceeding a channel capacity. However, Shannon's channel coding theorem proposes no detailed channel encoding/decoding method for supporting a data rate equivalent to the maximum channel capacity limit. Although a random code having a very large block size generally shows performance approximating a channel capacity limit of Shannon's channel coding theorem, when a Maximum A Posteriori (MAP) or Maximum Likelihood (ML) decoding scheme is used, it is not possible to implement the decoding scheme because of its heavy computation load.
The Turbo Code was proposed by Berrou, Glavieux, and Thitimajshima in 1993, and it has superior performance for approximating a channel capacity limit of Shannon's channel coding theorem. The proposal for use of the Turbo Code triggered active research on iterative decoding and graphical expression of codes. LDPC codes proposed by Gallager in 1962 have been newly spotlighted in that research. Cycles exist on a factor graph of the Turbo Code and the LDPC code, and it is well known that iterative decoding on the factor graph of the LDPC code where cycles exist is sub-optimal. The term “cycle” refers to a loop formed by edges connecting the variable nodes to the check nodes in a factor graph of a LDPC Code, and a length of the cycle is defined as the number of edges forming the loop. It has also been proven through experiments that the LDPC code has excellent performance through iterative decoding. The LDPC code known to have the highest performance ever shows performance having a difference of only about 0.04 [dB] at a channel capacity limit of Shannon's channel coding theorem at a Bit Error Rate (BER) of 10−5, using a block size of 107. In addition, although an LDPC code defined in Galois Field (GF) with q>2, i.e., GF(q) increases in complexity in its decoding process, it is much superior in performance to a binary code. However, there has been provided no satisfactory theoretical description of successful decoding by an iterative decoding algorithm for the LDPC code defined in GF (q).
The LDPC code proposed by Gallager is defined by a parity check matrix in which major elements have a value of 0 and minor elements except for the elements having the value of 0 have a value of 1. For example, an (N, j, k) LDPC code is a Linear Block code having a block length N, and is defined by a sparse parity check matrix in which each column has j elements having a value of 1, each row has k elements having a value of 1, and all of the elements except for the elements having the value of 1 all have a value of 0.
A regular LDPC code is an LDPC code in which a weight of each column in the parity check matrix is fixed to j and a weight of each row in the parity check matrix is fixed to k. Herein, the term “weight” refers to the number of elements having a non-zero value among the elements forming a generation matrix and a parity check matrix. Unlike the regular LDPC code, an irregular LDPC code is an LDPC code in which the weight of each column in the parity check matrix or the weight of each row in the parity check matrix is not fixed. It is generally known that the irregular LDPC code outperforms the regular LDPC code. In the irregular LDPC code the weight of each column or the weight of each row in the parity check matrix are not fixed, they are irregular. Consequently, the weight of each column in the parity check matrix or the weight of each row in the parity check matrix must be properly adjusted in order to guarantee the superior performance of the irregular LDPC code.
Referring to FIG. 1, a below is description of a parity check matrix of an (8, 2, 4) LDPC code as an example of an (N, j, k) LDPC code.
FIG. 1 illustrates a parity check matrix of a general (8, 2, 4) LDPC code.
Referring to FIG. 1, a parity check matrix H of the (8, 2, 4) LDPC code includes 8 columns and 4 rows in which a weight of each column is fixed to 2 and a weight of each row is fixed to 4. Since the weight of each column and the weight of each row in the parity check matrix are regular, the (8, 2, 4) LDPC code illustrated in FIG. 1 becomes a regular LDPC code.
FIG. 2 illustrates a factor graph of the (8, 2, 4) LDPC code of FIG. 1. Referring to FIG. 2, the factor graph of the (8, 2, 4) LDPC code includes 8 variable nodes of x1 211, x2 213, x3 215, x4 217, x5 219, x6 221, x7 223, and x8 225, and 4 check nodes 227, 229, 231, and 233. When an element having a value of 1, i.e., a non-zero value, exists at a point where an ith row and a jth column of the parity check matrix of the (8, 2, 4) LDPC code cross each other, a branch is created between a variable node xi and a jth check node.
Because the parity check matrix of the LDPC code has a very small weight as described above, it is possible to perform iterative decoding even in a Block code having a relatively long length, that exhibits performance approximating a capacity limit of a Shannon channel, such as a Turbo code, while continuously increasing a block length of the Block Code. MacKay and Neal have proven that the performance of an iterative decoding process of an LDPC code using a flow transfer scheme is approximate to an iterative decoding process of a Turbo Code.
In order to generate a high-performance LDPC code, the following conditions must be satisfied.
(1) Cycles on a factor graph of an LDPC code must be considered.
A cycle being long in length means that the number of edges connecting the variable nodes to the check nodes forming the loop in the factor graph of the LDPC code is large. In contrast, a cycle being short in length means that the number of edges connecting the variable nodes to the check nodes forming the loop in the factor graph of the LDPC code is small.
As cycles in the factor graph of the LDPC code become longer, the performance efficiency of the LDPC code increases for the following reasons. When long cycles are generated in the factor graph of the LDPC code, it is possible to prevent performance degradation such as an error floor occurring when too many cycles with a short length exist on the factor graph of the LDPC code.
(2) Efficient encoding of an LDPC code must be considered.
It is difficult for the LDPC code to undergo real-time encoding as compared with a Convolutional Code or a Turbo Code because of its high encoding complexity. To reduce the encoding complexity of the LDPC code, a Repeat Accumulate (RA) code has been proposed. However, the RA code also has a limitation in reducing the encoding complexity of the LDPC code. Therefore, consideration must be given to efficient encoding of the LDPC code.
(3) A degree distribution on a factor graph of an LDPC code must be considered.
Generally, an irregular LDPC code outperforms a regular LDPC code, because a factor graph of the irregular LDPC code has various degrees. The term “degree” refers to the number of edges connected to the nodes, i.e., the variable nodes and the check nodes, in the factor graph of the LDPC code. The phrase “degree distribution” on a factor graph of an LDPC code refers to a ratio of the number of nodes having a particular degree to the total number of nodes. It has been proven by Richardson that an LDPC code having a particular degree distribution is superior in performance.
However, no concrete channel interleaving/deinterleaving method based on characteristics of an LDPC code has been considered in the conventional communication system using the LDPC code. Accordingly, there exists a need exists for a concrete channel interleaving/deinterleaving method based on characteristics of an LDPC code in the conventional communication system using the LDPC code.